1. Field of the Invention
This invention relates to a data memory system, and more particularly to a data memory system having a semiconductor memory which includes an error detection/correction unit.
2. Description of the Related Art
As one of semiconductor memories, a nonvolatile semiconductor memory which stores information according to a charge amount in the charge storage layer, measures a variation in the conductance of a MOSFET according to the charge amount and reads out information is developed. This is a so-called EEPROM.
The EEPROM data readout system is a so-called non-destructive readout system which is not accompanied by destruction of data, unlike the case of a DRAM. That is, the EEPROM permits the data readout operation to be performed a plurality of times without destroying data. However, if the program operation and the erase operation are repeatedly performed, the following states (1) and (2) occur and data is destroyed.
(1) For example, the tunnel insulating film of the EEPROM is degraded, a leakage current increases and the charge holding characteristic is deteriorated.
(2) Charges are trapped in the tunnel insulating film and the threshold voltage of the EEPROM cell is set outside a preset range. Thus, so-called bit destruction occurs. As the memory capacity of the EEPROM increases, the probability that the EEPROM will contain bits subjected to bit destruction (the rate of occurrence of faulty bits) becomes higher. This is true even if the numbers of program operations and erase operations are constant.
One of the measures to counter the bit destruction is described in Japanese Patent Specification No. 3176019 (which is hereinafter referred to as a document 1), for example. The document 1 discloses a technique for reading out a memory cluster configured by a plurality of pages and detecting faulty bits when it is not required to read out data from an external I/O, for example, at the power supply turn ON or OFF time by use of an error detection/correction unit (Error Correction Code circuit: ECC circuit). If errors of a number exceeding the error reference value are detected, whole data items of the memory cluster to be subjected to the ECC process are read out and programmed into another memory area. Thus, the rate of occurrence of faulty bits as viewed from an external interface can be lowered.
Document 1: Japanese Patent Specification 3176019